The present invention relates to a MOS transistor logic circuit and, more particularly, to an output circuit for a high speed and low power logic circuit.
There are two types of logic circuits. One of them is a complementary MOS transistor logic circuit and the other is a single channel MOS transistor logic circuit, and in particular an N-channel device. The complementary MOS transistor logic circuit uses P- and N-channel MOS FET's and has an advantage of a low power consumption, but has a disadvantage of a relatively low speed operation. This is because of P-channel MOS transistor has a switching speed which is slower than that of an N-channel MOS transistor. In particular, a logic circuit including a plurality of P-channel MOS transistors connected in series between a power supply terminal and an output terminal requires a considerably long switching time. In contrast, the N-channel MOS transistor logic circuit uses enhancement and depletion type MOS FET's and has an advantage of high speed operation. However, the logic circuit employing enhancement and depletion N-channel MOS transistors has a disadvantage since it requires large power consumption.
As a high speed and low power logic circuit, therefore, a logic circuit is used that employs only enhancement N-channel MOS transistors driven in a push-pull manner with power supplied between higher and lower power supply voltages. However, such a logic circuit has a disadvantage since the logic high level of an output signal produced therefrom does not reach the higher power supply voltage, although the logic low level of the output signal reaches the lower power supply voltage. This is because a MOS transistor exists whose source is connected to an output terminal and whose drain is connected to a power supply terminal supplied with the higher power supply voltage. The logic high level of the output signal therefore becomes lower than the higher power supply voltage by a threshold voltage of the used transistor. A so-called bootstrap circuit is often employed to raise the logic high level of the output signal up to the higher power supply voltage. However, the bootstrap circuit lowers the operation speed of the logic circuit. Therefore, a level conversion circuit is added as an output circuit, in place of using the bootstrap circuit, to convert the logic high level of the output signal into a voltage level equal to the higher power supply voltage.
A complementary MOS (C-MOS) inverter is well known in the art as a level conversion circuit. The C-MOS inverter consists of P-channel and N-channel MOS transistors connected in series between the higher and lower power terminals, and the output signal produced from the logic circuit is applied to the gates of these transistors. The high level of the output signal turns the N-channel transistor ON and the low level thereof turns the P-channel transistor ON. As a result, the output signal from the logic circuit is widened to have an amplitude between the first and second power supply voltages.
It should be noted that the logic high level of the output signal is still slightly lower than the first power supply voltage. For this reason, the conductive resistance of the N-channel transistor is relatively large and thus reduces the load driving capability thereof. The operation speed for changing the output signal from the higher power supply voltage to the lower power supply voltage is thereby reduced. Moreover, the C-MOS inverter operates as an additional gate circuit, so that the above changing speed is further reduced.